AI Chip Stocks Valuation

The pricing setup for AI silicon in 2026 is no longer a single story. Training-cluster economics — large customers, lumpy capex, software stacks locked into specific accelerators — and inference economics — high-volume, cost-per-token sensitive, mixed-vendor supply — are diverging. The hub on this page covers six tickers across three layers: training accelerators (NVIDIA, AMD), AI networking silicon (Broadcom, Marvell), and mobile and edge IP (Qualcomm, Arm). Each is exposed differently to the bifurcation, and the reverse-DCF assumptions on the per-stock pages reflect those exposures unevenly.

Training accelerators: the moat is still software, but it is being tested

NVIDIA's data-center revenue compounded from approximately $15B in FY23 (year ending January 2023) to roughly $115B in FY25 — a 7x increase in two years. Gross margin held above 75%. The economics rest on three concentric advantages. Silicon: Hopper, then Blackwell across 2024–2025, then Rubin from 2026. Interconnect: NVLink for in-cluster, plus the Mellanox-derived InfiniBand franchise and the newer Spectrum-X Ethernet stack for AI fabrics. Software: CUDA, with the Megatron, TensorRT, Triton, and NeMo layers above it. Switching costs at hyperscaler training clusters run into thousands of engineer-years of accumulated optimization. Even when AMD MI300 silicon performs comparably on selected workloads, the porting cost gives NVIDIA pricing tolerance through the training stack.

AMD's MI300 series (MI300X, MI325X, MI350 in 2025, MI400 expected 2026) has been the only meaningful share-take story in merchant accelerators. Consensus mid-2025 estimates place AMD data-center GPU revenue in the high-single-digit billions for calendar 2025, roughly 5% of NVIDIA scale. The catch-up path runs through ROCm software maturity (the Linux-side answer to CUDA, still behind in framework coverage and operator support) and through Microsoft, Meta, and Oracle willingness to dual-source for inference workloads, where switching cost is materially lower than for training. Reverse DCF on the AMD TickerVal page implies a high-teens FCF CAGR — which is asking for share to compound from here, not for current share to maintain.

The under-discussed competitor in the training layer is hyperscaler internal silicon. Google TPU v5e and v5p, AWS Trainium2 and Trainium3 (the latter expected late 2025), Meta MTIA, and Microsoft Maia 100 and 200 are all in production. None has displaced NVIDIA at the leading edge for general-purpose training, but each reduces dependence on merchant accelerators for specific internal workloads. The signal to track is the merchant-GPU versus internal-silicon split inside hyperscaler capex commentary across 2026 and 2027.

AI networking silicon: the merchant beneficiary of internal-silicon programs

Broadcom is now the structural merchant beneficiary of hyperscaler internal-silicon. The custom line — XPU work for Google, accelerator ASIC for Meta, networking ASIC for AWS — booked roughly $12.2B in 2024, up from low-single-digit billions two years earlier. Gross margin sustained above 65%. The flywheel runs through process access: hyperscalers want internal silicon for cost and IP control, but the program needs a partner with TSMC N3 and N2 access, leading-edge SerDes IP, and CoWoS packaging slot allocation. Broadcom's switching ASIC franchise (Tomahawk for data-center switches, Jericho for routers) gives the company the SerDes and PHY portfolio that hyperscaler internal silicon programs require.

Marvell traces the same shape at smaller scale. Data-center silicon exited 2025 near a $3B run-rate per company commentary, with Inphi-derived optical DSP and Innovium-derived switching silicon as the layer-cake. Hyperscaler custom-silicon engagements with Amazon and Microsoft have been disclosed but not sized; the merchant-versus-custom mix is the opaque variable in the reverse-DCF assumption. Both stocks are exposed to the same hyperscaler-internal-silicon thread, but at very different scales — AVGO with established XPU programs and a deeper switching franchise, MRVL with optical and custom silicon ramping into a smaller revenue base.

Mobile and edge IP: handset is mature, royalty leverage compounds with node mix

Qualcomm sits structurally lower-growth than the rest of the hub. Handset is a mature franchise — global smartphone unit shipments have run roughly flat at 1.1–1.2 billion for several years — and ASP gains are gated on premium share. The upside thesis has two pieces: Snapdragon X Elite PC adoption against AMD and Intel x86 with Microsoft Copilot+ branding as a near-term distribution tailwind, and Snapdragon Ride automotive design wins where the design-in cycle is multi-year and the revenue lag is long. Reverse DCF on the QCOM TickerVal page implies a single-digit FCF CAGR — meaningfully more conservative than the rest of this hub.

Arm Holdings is the leverage point with limited correlation to wafer cycles. Licensing revenue runs at roughly 50% operating margin on $3.4B FY24 revenue, and royalty per device is set by lithography node, so a fleet shift from N5 and N4 toward N3 and N2 lifts royalty per chip regardless of unit-volume direction. Arm's exposure to AI compute is indirect but real: NVIDIA Grace, AWS Graviton, Microsoft Cobalt, and most hyperscaler internal silicon designs embed Arm cores. The IP-licensing business model gives Arm asymmetric upside if hyperscaler internal silicon takes share from x86 — Arm collects on each design regardless of which silicon provider wins.

What the page is implying right now

5-year P/E percentile sits in the upper deciles for NVDA, AVGO, and ARM. AMD reads in the middle of its range. QCOM sits below its 5-year median, consistent with handset-cycle skepticism. Reverse DCF implied FCF CAGR for the merchant accelerator and custom-silicon names (NVDA, AMD, AVGO) reaches the upper edge of the 5-year range — the same algebraic statement as elsewhere in TickerVal, that AI-cycle revenue durability is being priced through the explicit forecast window. Arm's percentile reads similarly elevated on a much shorter listed history (post-2023 IPO), and the reverse DCF reflects the licensing model leverage rather than unit-volume risk.

Tensions worth tracking

First and largest, the CUDA moat is being tested on three vectors simultaneously: AMD ROCm framework parity (slow but improving — Llama and DeepSeek inference port progress is the leading indicator), open-source compiler stacks (Triton, IREE, MLIR — pulling workloads off proprietary CUDA primitives), and hyperscaler internal silicon (where the moat is irrelevant by construction). The reverse DCF on NVIDIA implicitly bets that this multi-vector pressure does not compound faster than the Blackwell and Rubin generation cadence can extend per-accelerator value.

Second, hyperscaler capex split. The single most informative leading indicator for this hub is the merchant-GPU versus internal-silicon mix inside Microsoft, Meta, Google, and Oracle quarterly commentary. A material shift toward internal silicon for inference compresses NVIDIA pricing power on inference SKUs much more than it compresses Broadcom's custom-silicon backlog growth — the two stocks have correlated exposure on the surface but diverging signs of impact under that scenario.

Third, inference cost-per-token economics. As generative AI workloads migrate from training (lumpy, peak-FLOPS-driven) toward production inference (steady, cost-per-token sensitive), the merchant-GPU profile changes. Inference runs on Hopper L40S, on AMD MI325X, on hyperscaler internal silicon, and on edge silicon (Qualcomm Snapdragon AI, Apple Neural Engine), each at very different price points. Whether inference is dominated by the hyperscaler-internal-silicon case (cost-led) or the edge case (latency and privacy-led) is the variable that connects QCOM's edge-AI thesis to the AVGO and MRVL custom-silicon path.

Research reference only. Not investment advice. Source: SEC EDGAR. The actual valuation work happens on each stock's detail page, where reverse-DCF inputs, model suitability, and source-trace coverage can be inspected directly.